Summary

The paper introduces ClosNN, a proposed high-radix, multi-stage Network-on-Chip (NoC) architecture developed by Teknostra Engineering Pvt Ltd to address the growing communication demands of modern AI accelerators.

As AI workloads become increasingly distributed and communication-intensive, conventional Mesh-based NoC architectures can encounter limitations involving network congestion, endpoint bandwidth, communication latency and resource utilization. These challenges are particularly relevant to Transformer models, Mixture-of-Experts (MoE) architectures, collective communication and other distributed AI workloads.

ClosNN explores an alternative approach based on a Folded Clos network organization, integrating four principal architectural mechanisms:

1. High-Radix Multi-Stage Topology: Provides multiple global communication paths and aims to reduce network diameter and intermediate routing overhead.

• . Active-Active Multi-Homing: Connects selected high-traffic processing elements through multiple independent network attachments to increase endpoint connectivity and alleviate localized bandwidth bottlenecks.

3. Virtual-Channel Segregation: Separates different classes of network traffic to improve resource allocation and reduce Head-of-Line blocking.

4. Hybrid Congestion-Aware Routing: Combines global path distribution with adaptive routing fallback to respond to changing network congestion conditions.

Preliminary Simulation Findings

In a documented 64-node MoE gating simulation, ClosNN demonstrated:

• Approximately 90% higher throughput compared with the evaluated 2D Mesh baseline.
• Approximately 76% lower average latency compared with the same baseline.
• A maximum network diameter of three forwarding hops in the evaluated configuration.
• Preliminary modeled opportunities for reducing buffer area and dynamic communication energy.

These results indicate the potential benefits of combining topology-level path diversity, endpoint-level connectivity expansion and adaptive routing.

Development Roadmap

The research is progressing toward hardware validation through:

• Further simulation and workload benchmarking.
• SystemVerilog RTL development.